Aligning with the start of the new school year of 2025, CERN team took part in Fast Machine Learning for Science conference in Zürich with HLS4ML tutorial.
FPGAs provide unique advantages in the realm of machine learning acceleration. Unlike CPUs and GPUs, FPGAs allow for custom parallelism, data type precision and dataflow tailored specifically to the workload. Their reconfigurability enables the design of optimised hardware circuits that can reduce latency, power consumption, and improve throughput. Some common examples of FPGA-accelerated neural networks include particle classification, in-network traffic sniffing, and image segmentation for autonomous vehicles.
In this tutorial, authors introduce and hold a hands-on demo on hls4ml, an open-source library for real-time deployment of neural networks on FPGAs. hls4ml allows a seamless conversion from high-level models (e.g., from Keras or PyTorch) to low-latency, low-power FPGA designs. The tutorial covers the design choices behind hls4ml, from deeply pipelined dataflow architectures to model quantization and pruning. The hands-on demo allows participants to experiment with hls4ml’s Python API. Finally, the tutorial concludes with a live demo of the model inference on a real FPGA.
