The project’s consortium partner CERN presented HLS4ML use in Edge-SpAIce during the FPGA Developer Forum (FDF) on 29th May 2026 at CERN.
This HLS4ML tutorial provides a practical introduction to hls4ml for FPGA-based machine learning inference. It goes through the main hls4ml workflow using small neural network examples, teaches how key configuration choices affect latency and resource usage, and explore basic optimization techniques such as quantization and pruning.
The hands-on parts of the tutorial run on a CERN-curated Jupyter notebook platform. The session is designed as a practical first workflow rather than a complete FPGA architecture or hls4ml developer-level course.
